An open-loop DLL-based multi-phase clock generator for low jitter applications is designed in 0.13Âµm CMOS technology. A noise-free all-digital locking detection
circuitry (AD-LDC) is designed to detect whether the DLL is locked in time domain. Besides, a current-mismatch free, supplyregulated charge pump is also proposed. As the DLL operating in the open-loop mode, an rms jitter of 500 fs is achieved at the frequency of 400 MHz. The entire circuit occupies 0.01 mm2 and consumes 14 mW. The low jitter multi-phase clock generator can be applied for high-speed ADCs/DACs and wire line transceivers.
Proceedings of the 27th International Technical Conference on Circuits/Systems, Computers and Communications