English  |  正體中文  |  简体中文  |  Items with full text/Total items : 62568/95224 (66%)
Visitors : 2528420      Online Users : 257
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/81393

    Title: Test Slice Difference Technique for Low-Transition Test Data Compression
    Authors: Rau, Jiann-Chyi;Wu, Po-Han;Li, Wei-Lin
    Contributors: 淡江大學電機工程學系
    Keywords: Test Data Compression;Low Power Testing;VLSI;Design for Testability (DFT)
    Date: 2012-06-01
    Issue Date: 2013-03-11 16:00:16 (UTC+8)
    Publisher: Taipei: Tamkang University
    Abstract: This paper presents a low power strategy for test data compression and a new decompression
    scheme for test vectors. In our method, we propose an efficient algorithm for scan chain reordering to deal with the power dissipation problem. Further, we also propose a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one extra scan cell. In experimental results, the scheme that we presented achieve high compression ratio. The power consumption is also better compared with other well-known compression techniques.
    Relation: Journal of Applied Science and Engineering 15(2), pp.157-166
    DOI: 10.6180/jase.2012.15.2.09
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

    Files in This Item:

    File Description SizeFormat

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback