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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/81366


    Title: Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform
    Authors: Hsia, Chih-Hsien;Chiang, Jen-Shiun;Guo, Jing-Ming
    Contributors: 淡江大學電機工程學系
    Keywords: 2-D dual-mode lifting-based discrete wavelet transform;JPEG2000;low-transpose memory
    Date: 2013-04
    Issue Date: 2013-03-11 13:43:17 (UTC+8)
    Publisher: Piscataway:Institute of Electrical and Electronics Engineers
    Abstract: Memory requirements (for storing intermediate signals) and critical path are the essential issues for two-dimensional (2-D) (or multi-dimensional) transforms. This work presents new algorithms and hardware architectures to address the above issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) Lifting-based Discrete Wavelet Transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the merits of low-transpose memory, low latency, and regular signal flow, making it suited for VLSI implementation. The transpose memory requirement of the N×N 2-D 5/3 mode LDWT and 2-D 9/7 mode LDWT are 2N and 4N, respectively. Comparison results indicate that the proposed hardware architecture has a lower lifting-based low-transpose memory size requirement than the previous architectures. As a result, it can be applied to real-time visual operations such as JPEG2000, Motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding (SVC) applications.
    Relation: IEEE Transactions on Circuits and Systems for Video Technology 23(4), pp.671-683
    DOI: 10.1109/TCSVT.2012.2211953
    Appears in Collections:[電機工程學系暨研究所] 期刊論文

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