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    題名: Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application
    作者: Yang, Wei-Bin;Wang, Chi Hsiung;Chang, Hsiang Hsiung;Hong, Ming Hao;Shen, Jsung Mo
    貢獻者: 淡江大學電機工程學系
    日期: 2013-01-01
    上傳時間: 2013-03-08 17:13:45 (UTC+8)
    出版者: Switzerland: Trans Tech Publications
    摘要: This paper presents a low-power fast-settling low-dropout regulator (LDO) using a digitally assisted voltage accelerator. Using the selectable-voltage control technique and digitally assisted voltage accelerator significantly improves the transition response time within output voltage switched. The proposed LDO regulator uses the selectable-voltage control technique to provide two selectable-voltage outputs of 2.5 V and 1.8 V. Using the digitally assisted voltage accelerator when the output voltage is switched reduces the settling time. The simulation results show that the settling time of the proposed LDO regulator is significantly reduced from 4.2 ms to 15.5 μs. Moreover, the selectable-voltage control unit and the digitally assisted voltage accelerator of the proposed LDO regulator consume only 0.54 mW under a load current of 100 mA. Therefore, the proposed LDO regulator is suitable for low-power dynamic voltage and frequency-scaling applications.
    關聯: Applied Mechanics and Materials 284-287, pp.2526-2530
    DOI: 10.4028/www.scientific.net/AMM.284-287.2526
    顯示於類別:[電機工程學系暨研究所] 期刊論文

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