A new phase interpolator circuit for frequency multiplication design in embedded system

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/81309

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題名:	A new phase interpolator circuit for frequency multiplication design in embedded system
作者:	Yang, Wei-Bin;Wang, Chi-Hsiung;Xie, Shao-Jyun
貢獻者:	淡江大學電機工程學系
日期:	2013-03
上傳時間:	2013-03-08 17:08:26 (UTC+8)
出版者:	Japan: ICIC International
摘要:	The new phase interpolator circuit is proposed to double the clock frequency up to 480MHz for USB application in embedded system. The most crucial purpose is ensuring that the interpolated signal rises precisely at one-half of time interval between two complementary signals. The proposed circuit was fabricated in a 0.35μm 1P2M complementary metal-oxide-semiconductor (CMOS) process and works with a supply voltage of 3.3V. By Hspice simulation result, the measured output frequency is 480MHz with 240MHz input clock frequency. The measured jitter performance and power consumption is 10.7ps and 2.6mW, respectively. Therefore, the proposed phase interpolator circuit can be applied to 480MHz USB devices.
關聯:	ICIC Express Letters 7(3A), pp.831-837
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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