A new phase interpolator circuit for frequency multiplication design in embedded system

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/81309

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Title:	A new phase interpolator circuit for frequency multiplication design in embedded system
Authors:	Yang, Wei-Bin;Wang, Chi-Hsiung;Xie, Shao-Jyun
Contributors:	淡江大學電機工程學系
Date:	2013-03
Issue Date:	2013-03-08 17:08:26 (UTC+8)
Publisher:	Japan: ICIC International
Abstract:	The new phase interpolator circuit is proposed to double the clock frequency up to 480MHz for USB application in embedded system. The most crucial purpose is ensuring that the interpolated signal rises precisely at one-half of time interval between two complementary signals. The proposed circuit was fabricated in a 0.35μm 1P2M complementary metal-oxide-semiconductor (CMOS) process and works with a supply voltage of 3.3V. By Hspice simulation result, the measured output frequency is 480MHz with 240MHz input clock frequency. The measured jitter performance and power consumption is 10.7ps and 2.6mW, respectively. Therefore, the proposed phase interpolator circuit can be applied to 480MHz USB devices.
Relation:	ICIC Express Letters 7(3A), pp.831-837
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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