Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000

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題名:	Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000
作者:	Li, Wei-ming;Hsia, Chih-Hsien;Chiang, Jen-Shiun
貢獻者:	淡江大學電機工程學系
日期:	2009
上傳時間:	2013-03-07 14:02:17 (UTC+8)
出版者:	New York: Institute of Electrical and Electronics Engineers (IEEE)
摘要:	In this work, we propose a memory-efficient architecture of lifting based two-dimensional discrete wavelet transform (2D DWT) for motion-JPEG2000. The proposed 2D DWT architecture consists of a 1D row processor, internal memory, and a 1D column processor. The main advantage of this 2D DWT is to reduce the internal memory requirement significantly. For an NtimesN image, only 2N and 4N sizes of internal memory are required for the 5/3 and 9/7 filters, respectively, to perform the one-level 2D DWT decomposition. Moreover, it supports both lossless and lossy operation for 5/3 and 9/7 filters with high operation speed. The proposed 2D DWT surpasses the existed lifting-based designs in the aspects of low internal memory requirement. It is suitable for VLSI implementation and can support various real-time image/video applications such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
關聯:	Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp.750-753
DOI:	10.1109/ISCAS.2009.5117857
顯示於類別:	[電機工程學系暨研究所] 會議論文

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