English  |  正體中文  |  简体中文  |  Items with full text/Total items : 57517/91034 (63%)
Visitors : 13431451      Online Users : 312
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/80831

    Title: Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000
    Authors: Li, Wei-ming;Hsia, Chih-Hsien;Chiang, Jen-Shiun
    Contributors: 淡江大學電機工程學系
    Date: 2009
    Issue Date: 2013-03-07 14:02:17 (UTC+8)
    Publisher: New York: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: In this work, we propose a memory-efficient architecture of lifting based two-dimensional discrete wavelet transform (2D DWT) for motion-JPEG2000. The proposed 2D DWT architecture consists of a 1D row processor, internal memory, and a 1D column processor. The main advantage of this 2D DWT is to reduce the internal memory requirement significantly. For an NtimesN image, only 2N and 4N sizes of internal memory are required for the 5/3 and 9/7 filters, respectively, to perform the one-level 2D DWT decomposition. Moreover, it supports both lossless and lossy operation for 5/3 and 9/7 filters with high operation speed. The proposed 2D DWT surpasses the existed lifting-based designs in the aspects of low internal memory requirement. It is suitable for VLSI implementation and can support various real-time image/video applications such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
    Relation: Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp.750-753
    DOI: 10.1109/ISCAS.2009.5117857
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

    Files in This Item:

    File Description SizeFormat
    Memory-Efficient Architecture of 2-D Dual-Mode.pdf全文檔971KbAdobe PDF387View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback