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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/80822


    Title: New memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform for JPEG2000
    Authors: Hsia, Chih-Hsien;Chiang, Jen-Shiun
    Contributors: 淡江大學電機工程學系
    Keywords: 2-D 5/3 mode LDWT;2-D 9/7 mode LDWT;interlaced read scan algorithm (IRSA);lifting-based discrete wavelet transform (LDWT);low-transpose memory
    Date: 2008
    Issue Date: 2013-03-07 14:01:41 (UTC+8)
    Publisher: New York: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: This work presents new algorithms and hardware architectures to improve the critical issues of the 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the advantages of low-transpose memory, low latency, and regular signal flow, which is suitable for VLSI implementation. The transpose memory requirement of the N ?? N 2-D 5/3 mode LDWT is 2N, and that of 2-D 9/7 mode LDWT is 4N. According to the comparison results, the proposed hardware architecture surpasses previous architectures in the aspects of lifting-based low-transpose memory size. It can be applied to real-time visual operations such as JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
    Relation: Communication Systems, 2008. ICCS 2008. 11th IEEE Singapore International Conference on, pp.766-772
    DOI: 10.1109/ICCS.2008.4737288
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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