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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/80821

    Title: 應用於 H.264/AVC 之高效能去方塊濾波器硬體架構設計
    Authors: 夏至賢;Hsia, Chih-Hsien;江正雄;陳延任
    Contributors: 淡江大學電機工程學系
    Date: 2007
    Issue Date: 2013-03-07 14:01:37 (UTC+8)
    Abstract: 在影像解碼階段,去方塊濾波器(deblocking filter)需要相當大的運算量,若是完全以軟體計算,將會佔用大量的系統頻寬,因此,設計一個硬體架構成為目前很重要的一個問題。本論文中,我們提出一個低記憶體空間且低成本之有效的去方塊濾波器架構以減低去方塊濾波器運算時間,同時降低系統匯流排的使用。相較於先前所提出的硬體架構,我們提出藉由雙埠靜態隨機存取記憶體(dual-port SRAM)及兩個埠的靜態隨機存取記憶體(two-port SRAM)架構,使用新的資料讀取方式來儲存資料,如此可省下轉置記憶體的使用,使硬體面積較小;同時配合平行處理單元,來加速處理速度的提升。
    Relation: 第五屆現代通訊科技應用學術研討會論文集=Proceedings of the 5th Conference on Communication Application, 6p.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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