Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/80543

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/80543

题名:	Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
作者:	Shih, Chi-Jih;Hsu, Chih-Yao;Kuo, Chun-Yi;Li, James;Rau, Jiann-Chyi;Krishnendu Chakrabarty
贡献者:	淡江大學電機工程學系
日期:	2012-11-28
上传时间:	2013-01-31 10:49:33 (UTC+8)
出版者:	New York: Hindawi Publishing
摘要:	Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC.
關聯:	Active and Passive Electronic Components 2012, 763572
DOI:	10.1155/2012/763572
显示于类别:	[電機工程學系暨研究所] 期刊論文

文件中的档案:

档案	描述	大小	格式	浏览次数
1563-5031_2012p763572(10pages).pdf		2037Kb	Adobe PDF	331	检视/开启
index.html		0Kb	HTML	230	检视/开启

在機構典藏中所有的数据项都受到原著作权保护.

TAIR相关文章