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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/80543

    Title: Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
    Authors: Shih, Chi-Jih;Hsu, Chih-Yao;Kuo, Chun-Yi;Li, James;Rau, Jiann-Chyi;Krishnendu Chakrabarty
    Contributors: 淡江大學電機工程學系
    Date: 2012-10-18
    Issue Date: 2013-01-31 10:49:33 (UTC+8)
    Publisher: New York: Hindawi Publishing
    Abstract: Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC.
    Relation: Active and Passive Electronic Components 2012, 763572(10pages)
    DOI: 10.1155/2012/763572
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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