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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/80364


    Title: Hardware Accelerator Design for Image Processing
    Authors: Li, S.A.;Wong, C.C.;Yang, C.Y.;Chen, L.F.
    Contributors: 淡江大學電機工程學系
    Keywords: FPGA;human-machine interface;hardware accelerator
    Date: 2012-08
    Issue Date: 2013-01-23 11:04:14 (UTC+8)
    Publisher: Berlin: Springer Berlin Heidelberg
    Abstract: This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.
    Relation: Lecture Notes in Computer Science 7429, pp.436-437
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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