Ant Colony Optimization algorithm design and its FPGA implementation

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/80317

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題名:	Ant Colony Optimization algorithm design and its FPGA implementation
作者:	Li, S.A.;Yang, M.H.;Weng, C.W.;Chen, Y.H.;Lo, C.H.;Wu, C.E.;Wong, C.C.
貢獻者:	淡江大學電機工程學系
關鍵詞:	Ant Colony Algorithm;FPGA;Hardware/Software Codesign;SOPC
日期:	2012-11
上傳時間:	2013-01-21 22:06:00 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	In this paper, a Hardware/Software (HW/SW) co-design method of ant colony optimization (ACO) algorithm is proposed to implement on the FPGA chip. In this paper, the software is designed with C language and hardware is designed with Verilog hardware description language (HDL). The HW/SW co-design method is a technique based on a SOPC (System on a Programmable Chip). In this paper, the path selecting and path analysis are designed in SOPC. The path selecting belongs to the pre-processing of the ACO algorithm and it cost a longer computing processing time. Therefore, a hardware circuit is designed to speed up processing. The path analysis will be designed by the C language within the NIOS II processor. In the experimental results, the processing time can be reduced by the proposed method.
關聯:	Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on, pp.262-265
DOI:	10.1109/ISPACS.2012.6473492
顯示於類別:	[電機工程學系暨研究所] 會議論文

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