Test Slice Difference Technique for Low-Transition Test Data Compression

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/78157

Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/78157

Title:	Test Slice Difference Technique for Low-Transition Test Data Compression
Authors:	饒建奇;吳柏翰;李威霖
Contributors:	淡江大學電機工程學系
Keywords:	Test Data Compression;Low Power Testing;VLSI;Design for Testability (DFT)
Date:	2012-06
Issue Date:	2012-09-07 18:53:55 (UTC+8)
Publisher:	Taiwan : Tamkang University
Abstract:	This paper presents a low power strategy for test data compression and a new decompression scheme for test vectors. In our method, we propose an efficient algorithm for scan chain reordering to deal with the power dissipation problem. Further, we also propose a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one extra scan cell. In experimental results, the scheme that we presented achieve high compression ratio. The power consumption is also better compared with other well-known compression techniques.
Relation:	淡江理工學刊 = Tamkang Journal of Science and Engineering 15(2), p.157-166
DOI:	10.6180/jase.2012.15.2.09
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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