Hardware accelerator design for image processing

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Title:	Hardware accelerator design for image processing
Authors:	Li, Shih-an;Wong, Ching-chang;Yang, Ching-yang;Chen, Li-feng
Contributors:	淡江大學電機工程學系
Keywords:	FPGA;human-machine interface;hardware accelerator
Date:	2012-08
Issue Date:	2012-09-04 14:30:59 (UTC+8)
Publisher:	Heidelberg : Springer Berlin
Abstract:	This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.
Relation:	Lecture Notes in Computer Science 7429,　p.436-437
DOI:	10.1007/978-3-642-32527-4_48
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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