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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/78137


    Title: A Novel SOPC-Based CMOS Image Sensor Testing System
    Authors: Li, Shin-an;Chiang, Jen-shiun;Chen, Kuang-yuan;Liu, Ta-kang;Wong, Ching-chang
    Contributors: 淡江大學電機工程學系
    Keywords: EMBEDDED PROCESSOR;FPGA;HW/SW CO-DESIGN;IMAGE ACCELERATOR;IMAGE PROCESS;SOPC
    Date: 2012-05-01
    Issue Date: 2012-09-04 13:56:01 (UTC+8)
    Publisher: Valencia: American Scientific Publishers
    Abstract: Since CMOS Image Sensor (CIS) has the characteristics of low cost and low power consumption as well as ease of integration with digital IC, the module size can thus be greatly reduced. Therefore, as the process evolutions, CMOS pixel capacity gets continuously enlarged, and it is thus wieldy used in all kinds of consumer products that need to record or detect the images. However, as the image quantity gets continuously enhanced, the test process of CIS gets more and more complicated, the needed test platform price and test time gets increased, which usually leads to serious burden on the test cost. The test procedure of CIS actually can be divided into traditional DC parameter test, functional test and the specific image test for CIS. However, the test platform associated the above two test functions hast is specific use, and the enhancement in the pixel capacity further leads to difficulty in reducing the test cost. This paper proposes a System On a Programmable Chip (SOPC) based CMOS image test platform to be associated with traditional function test platform to form a CIS test architecture. It not only can break the specific use of test platform, but also can reduce the test cost effectively. Moreover, due to the great reduction of image transmission distance, the image test quality can be greatly reduced.
    Relation: Sensor Letters 10(5-6), pp.1068-1074
    DOI: 10.1166/sl.2012.2287
    Appears in Collections:[電機工程學系暨研究所] 期刊論文

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