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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/77475

    Title: 新型內插電路應用於多頻率輸出之鎖相迴路
    Other Titles: A phase-locked loop with multi-frequency outputs by using new interpolator circuit
    Authors: 廖朝正;Liao, Chao-Cheng
    Contributors: 淡江大學電機工程學系碩士班
    楊維斌;Yang, Wei-Bin
    Keywords: 鎖相迴路;相位內插;多頻率輸出;Phase-Locked Loop;phase interpolate;interpolator;multi-frequency
    Date: 2012
    Issue Date: 2012-06-21 06:48:36 (UTC+8)
    Abstract: 由於製程演進及科技的進步,電路系統中所須的時脈訊號越來越快,晶片內部的非理想效應會使相位產生偏差延遲,導致資料結果錯誤,此時時脈同步的問題就非常重要,時脈同步的技術通常使用鎖相迴路(PLL)或是延遲鎖定迴路(DLL)來完成系統時脈的整合。
    (Frequency Synthesizer)、訊號與資料回復(Clock and Data Recovery,CDR)等應用。而在SOC(system on a chip)方面來看,也利用鎖相迴路中電壓控制振盪器的輸出頻率回授時的任意除頻器(÷N)來合成多個頻
    本論文是利用相位內插電路(Interpolator)在電壓控制振盪器(Voltage-Controlled Oscillator, VCO)的延遲級中不同的相位間做內插,產生更多不同的相位,再經過相位合成器合成出更多不同的頻率輸出,也可用於非整數除頻器上。論文中將提出新的內插電路,並應用在新的架構中,應用於在4 個相差90°相位中內插輸出12 個相差30°的相位,並合成6 倍頻以及許多非整數除頻。此PLL 系統輸入頻率14.318 MHz 可由晶體振盪產生,輸出可達800 MHz,適用於主機板上。
    With the extensive growth of the demand for high speed system, the required clock rate continues increasing. Thus, the issue of the clock synchronization in the subsystems
    becomes more and more important, which results in a great improvement on the clock skew and the data link technology. Phase-locked loop(PLL) and delay-locked loop(DLL) provide a well locking loop for the clock synchronization in the system.
    PLL has been widely used in various research fields, ex: frequency synthesizers, clock and data recovery and so on. In a system on a chip, clock generators are used the PLL to satisfied the demand, and the clock is used as multiple frequencies for subsystems.
    This paper describes a voltage controlled oscillator(VCO) and the interpolator combine to generate multiplier and fractional-n clock frequencies. In the paper, will provide a new interpolator in the new architecture, which is four different phase input and twelve phase output by interpolator. The input frequencies is 14.318 MHz and the output frequencies is 800MHz in the PLL system.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Thesis

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