Memory-efficient architecture of 2-D lifting-based discrete wavelet transform

doi:10.1080/02533839.2011.577601

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/77278

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Title:	Memory-efficient architecture of 2-D lifting-based discrete wavelet transform
Authors:	Hsia, Chih-Hsien;Li, Wei-Ming;Chiang, Jen-Shiun
Contributors:	淡江大學電機工程學系
Keywords:	lifting scheme;discrete wavelet transform (DWT);low internal memory;interlaced read scan architecture (IRSA)
Date:	2011-07
Issue Date:	2013-07-11 11:58:33 (UTC+8)
Publisher:	Abingdon: Taylor & Francis Ltd.
Abstract:	This article presents new hardware architectures to address critical issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding modes) lifting-based discrete wavelet transform (LDWT) for Motion-JPEG2000. The massive requirement of transpose memory is the most critical for LDWT. The proposed architecture can support high-resolution videos and reduce the internal memory requirement significantly. In our LDWT approach, the signal flow is revised from row-wise only to mixed row- and column-wise, and a new architecture, called interlaced read scan architecture (IRSA), is used to reduce the transpose memory. By the IRSA approach, the transpose memory size is only 2N or 4N (5/3 or 9/7 mode) for an N × N DWT. Besides, the proposed 2-D LDWT operates with parallel and pipelined schemes to increase the operation speed. It can be applied to real-time visual operations such as JPEG2000 and Motion-JPEG2000.
Relation:	Journal of the Chinese Institute of Engineers=中國工程學刊 34(5), pp.629-643
DOI:	10.1080/02533839.2011.577601
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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