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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/76745


    Title: 可加性白色高斯雜訊之硬體架構模擬與實現
    Authors: 李揚漢;詹益光;莊明學;曾憲威;林政曜;曾威傑
    Contributors: 淡江大學電機工程學系
    Keywords: 可加性白色高斯雜訊;位元錯誤率;信號雜訊比;迴旋碼編碼器;維特比解碼器;虛擬亂碼;AWGN;BER;SNR;Convolutional encoder;Viterbi decoder;PN code
    Date: 2005-11
    Issue Date: 2012-05-16 17:03:58 (UTC+8)
    Abstract: 在本論文中我們提出無線網路的可加性白色高斯雜訊(Additive white gaussian noise, AWGN)之硬體設計。信號在經過不同的通道調變系統下加入AWGN,也就是 與雜訊相加後所產生的信號,即真正所接收到的信號。我們將此信號與原本傳送 的信號相比較,計算出位元錯誤率(Bit error rate, BER)。在本論文中先用 Matlab模擬出在各種調變下經由信號雜訊比(Signal to noise ratio, SNR)的改 變來產生不同結果,再去驗證經由Pathfinder產生的硬體架構和模擬的結果是否 相同。此篇論文在於實現一AWGN的硬體架構設計及其在Pathfinder上模擬其量測 結果。
    Relation: 2005民生電子暨信號處理研討會論文集=Proceedings of Workshop on Consumer Electronics and Signal Processing,4頁
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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