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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/75307

    Title: The High-Performance and Low-Power CMOS Output Driver Design
    Authors: Yang, Wei-bin;Liao, Pei-hsuan;Wang, Chi-hsiung;Cheng, Ching-tsan
    Contributors: 淡江大學電機工程學系
    Date: 2011-06-20
    Issue Date: 2012-03-19 16:02:06 (UTC+8)
    Publisher: Nanchang University; Springer; IEEE IAS Nanchang Chapter
    Abstract: There are many important points for high-speed CMOS integrated circuit, such as switching speed, power dissipation and full-swing of voltage. In this paper, a group of high performance and low-power bootstrapped CMOS drivers are designed in order to reduce power consumption and enhance the speed of switch for driving a large load, where the drivers will reduce the power consumption by using bootstrap manipulate conditional to input statistics. Moreover, the low swing bootstrapped feedback controlled split path (LBFS) is conducted to reduce the dynamic power dissipation and limiting the voltage swing of gate of the output stage. Finally, the charge transfer feedback controlled split path (CRFS) CMOS buffer is used to restitute and pull down the gate voltage for reducing power consumption and line noise. According to the HSPICE simulation results, the proposed drivers of the CMOS driver are reduced by 20%~40 compared to the conventional design.
    Relation: 2011 International Conference on Electric and Electronics (EEIC 2011), Nanchang, China
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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