Hardware/Software Co-design for Particle Swarm Optimization Algorithm

doi:10.1109/ICSMC.2010.5641826

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題名:	Hardware/Software Co-design for Particle Swarm Optimization Algorithm
作者:	Li, Shih-an;Wong, Ching-chang;Yu, Chia-jun;Hsu, Chen-chien
貢獻者:	淡江大學電機工程學系
關鍵詞:	Field Programmable Gate Array (FPGA);HW/SW Co-design;Particle swarm optimization (PSO);system on a programmable chip (SOPC)
日期:	2010-10
上傳時間:	2012-03-16 21:27:11 (UTC+8)
出版者:	Institute of electrical and electronics engineers (IEEE)
摘要:	This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve the performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a particle updating accelerator module via hardware implementation for updating velocity and position of particles and a fitness evaluation module implemented on a soft-cored processor for evaluating the objective functions are respectively designed and work closely together to accelerate the evolution process. Thanks to a flexible design, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To compensate the deficiency in generating truly random numbers by hardware implementation, a particle re-initialization scheme is also presented in this paper to further improve the execution performance of the PSO. Experiment results have demonstrated that the proposed HW/SW co-design approach to realize PSO is capable of achieving a high-quality solution effectively.
關聯:	Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, pp.3762-3767
DOI:	10.1109/ICSMC.2010.5641826
顯示於類別:	[電機工程學系暨研究所] 會議論文

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