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    題名: 2.5-GHz hybrid oscillator with both a wide tuning range and high frequency resolution for digital PLL
    作者: 施鴻源;Chiu, Huan-ke;Chueh, Tzu-chan;Chen, Chiou-bang
    貢獻者: 淡江大學電機工程學系
    關鍵詞: ADPLL
    Oscillator;frequency synthesizer;varactor;phase noise;tuning range
    日期: 2011-04-15
    上傳時間: 2012-03-14 11:26:35 (UTC+8)
    出版者: IEEE
    摘要: A hybrid oscillator for WiMAX application is presented with comprehensive study. The hybrid oscillator is part of a digital fractional-N frequency synthesizer realized in a 0.13-um CMOS process. By operating the DAC followed by oscillator, the requirement of finest switched capacitor value and high-speed dithering of ǻӢ data converter are relaxed. A time-domain simulation approach for modeling the phase noise introduced by the frequency discretization was taken. The proposed approach is well suited to investigate complex interactions in the sophisticated system, which cannot be studied by using conventional RF and analog simulation tools. The prototype core chip consumes 8.6 mA from a 1.4-V supply while providing a phase noise of -120.35 dBc/Hz at 1 MHz offset from 2.808 GHz carrier and a 570 MHz frequency tuning range (23%).
    關聯: 2011 International Conference on Electric Information and Control Engineering (ICEICE), Wuhan, China, pp952-955
    DOI: 10.1109/ICEICE.2011.5777624
    顯示於類別:[電機工程學系暨研究所] 會議論文

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