Table-lookup approach for compiling two-level data-processor mappings in HPF

doi:10.1007/BFb0032682

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Title:	Table-lookup approach for compiling two-level data-processor mappings in HPF
Authors:	石貴平;Shih, Kuei-ping;Sheu, Jang-ping;Huang, Chua-huang
Contributors:	淡江大學資訊工程學系
Keywords:	Active Element;Array Element;Array Statement;Virtual Processor;Local Array
Date:	1997-08
Issue Date:	2011-10-24 11:43:01 (UTC+8)
Abstract:	This paper presents some compilation techniques to compress holes. Holes are the memory locations mapped by useless template cells and are caused by the non-unit alignment stride in a two-level dataprocessor mapping. In a two-level data-processor mapping, there is a repeated pattern for array elements mapped onto processors. We classify blocks into classes and use a class table to record the attributes of classes for the data distribution. Similarly, data distribution on a processor also has a repeated pattern. We use compression table to record the attributes of the first data distribution pattern on that processor. By using class table and compression table, hole compression can be easily and efficiently achieved. Compressing holes can save memory usage, improve spatial locality and further increase system performance. The proposed method is efficient, stable and easy implement. The experimental results do confirm the advantages of our proposed method over existing methods.
Relation:	International Workshop on Languages and Compilers for Parallel Computing (LCPC), Minnesota, USA
DOI:	10.1007/BFb0032682
Appears in Collections:	[Graduate Institute & Department of Computer Science and Information Engineering] Proceeding

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