English  |  正體中文  |  简体中文  |  Items with full text/Total items : 49287/83828 (59%)
Visitors : 7150196      Online Users : 41
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70594


    Title: VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications
    Authors: Chiang, Jen-Shiun;Hsia, Chih-Hsien;Chen, Hsin-Jung;Lo, Te-Jung
    Contributors: 淡江大學電機工程學系
    Date: 2005
    Issue Date: 2013-03-07 14:57:00 (UTC+8)
    Publisher: New York: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: The paper presents a low memory and high speed VLSI architecture for 2D lifting-based lossless 5/3 filter discrete wavelet transform (DWT). The architecture is based on the proposed interlaced read scan algorithm (IRSA) and parallel scheme processing to achieve low memory size and high speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity, transforming signal with extension, and regular data flow, and is suitable for VLSI implementation. It can be applied to real time image/video operation of JPEG2000 and MPEG-4 applications. Basing on the proposed architecture, we designed and simulated a 2D DWT VLSI chip by 0.35 弮m 1P4M CMOS technology. The memory requirement of the N?N 2D DWT is N, and it can operate at 100 MHz clock frequency.
    Relation: Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on Vol. 5, pp.4554-4557
    DOI: 10.1109/ISCAS.2005.1465645
    Appears in Collections:[電機工程學系暨研究所] 會議論文

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML178View/Open
    VLSI Architecture of Low Memory and High Speed.pdf194KbAdobe PDF175View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback