The new improved pseudo fractional-N clock generator with 50% duty cycle

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/70583

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題名:	The new improved pseudo fractional-N clock generator with 50% duty cycle
作者:	Kuo, Shu-chang;Hung, Tzu-chien;Yang, Wei-bin
貢獻者:	淡江大學電機工程學系
日期:	2006-05
上傳時間:	2011-10-23 21:27:58 (UTC+8)
摘要:	Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V
關聯:	2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
DOI:	10.1109/ISCAS.2006.1693547
顯示於類別:	[電機工程學系暨研究所] 會議論文

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