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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/70583

    Title: The new improved pseudo fractional-N clock generator with 50% duty cycle
    Authors: Kuo, Shu-chang;Hung, Tzu-chien;Yang, Wei-bin
    Contributors: 淡江大學電機工程學系
    Date: 2006-05
    Issue Date: 2011-10-23 21:27:58 (UTC+8)
    Abstract: Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V
    Relation: 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
    DOI: 10.1109/ISCAS.2006.1693547
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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