The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/70582

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题名:	The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle
作者:	Yang, Wei-bin;Kuo, Shu-chang;Chu, Yuan-hua;Cheng, Kuo-hsing
贡献者:	淡江大學電機工程學系
日期:	2005-08-29
上传时间:	2011-10-23 21:27:53 (UTC+8)
摘要:	Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.
關聯:	2005 European Conference on Circuit Theory and Design
DOI:	10.1109/ECCTD.2005.1523093
显示于类别:	[電機工程學系暨研究所] 會議論文

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