The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle

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Title:	The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle
Authors:	Yang, Wei-bin;Kuo, Shu-chang;Chu, Yuan-hua;Cheng, Kuo-hsing
Contributors:	淡江大學電機工程學系
Date:	2005-08-29
Issue Date:	2011-10-23 21:27:53 (UTC+8)
Abstract:	Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.
Relation:	2005 European Conference on Circuit Theory and Design
DOI:	10.1109/ECCTD.2005.1523093
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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