IEEE Circuits and Systems Society; National Cheng Kung University
This paper presents a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one scan cell. Consequently, hardware overhead is much lower than cyclical scan chains (CSR). As the complexity of VLSI continues to grow, excessive power supply noise has become seriously. We propose a new compression scheme which smooth down the switching activity and reduce the test data volume simultaneously.
Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.2986-2989