System-on-a-chip with multiple power domains reduces leakage power consumption by power gating which shut off the idle blocks. Power gating is an effective technology to reduce sub-threshold leakage current. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and make the technique not worth the effort. For example, power gating may cause instantaneous current when sleep transistors are turned on. And instantaneous current will lead to VDD voltage drop, ground bounce, and inductive noise in power supply line. To reduce the ground bounce, we proposed new power gating structures with added bulk controller when sleep transistors are turned on. Simulation results show that the maximum voltage fluctuations for our power gating structures are smaller than those for the other power gating structures. Our power gating structures reduce the instantaneous current and voltage fluctuations in the power supply line.
Relation:
2007 IEEE International Symposium on Circuits and Systems(ISCAS 2007), pp.3740 - 3743
