淡江大學機構典藏:Item 987654321/70493
English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 58323/91877 (63%)
造訪人次 : 14320964      線上人數 : 115
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70493


    題名: Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment
    作者: 饒建奇;Rau, Jiann-Chyi;Lin, Chu-Chuan;Wu, Po-Han;Chen, Gong-Han
    貢獻者: 淡江大學電機工程學系
    日期: 2010-05-30
    上傳時間: 2011-10-23 21:21:34 (UTC+8)
    出版者: IEEE
    摘要: We present a Linear Feedback Shift Register (LFSR) like architecture, because the LFSR can bring a lot of data by using a few bits. We calculate the ATE data by Gauss-Elimination and put the ATE data to our decompression architecture to generate a lot of patterns. And one ATE data will run several times in the architecture. If some faults cannot be detected, we will generate the patterns which are brought by fault simulation. If still a few faults cannot be detected, the faults will be caught by directly modify the bits of ATE data. The less ATE data we use, the less cycles we need. Because the reason, we can get high speed testing. And the less data, the low-cost environment we need. The cycle we can save is up to 61.60x. And the average rate of compression can get 19.33x.
    關聯: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, pp.437-440
    DOI: 10.1109/ISCAS.2010.5537677
    顯示於類別:[電機工程學系暨研究所] 會議論文

    文件中的檔案:

    沒有與此文件相關的檔案.

    在機構典藏中所有的資料項目都受到原著作權保護.

    TAIR相關文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋