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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70492

    Title: Multi-Chains Encoding Scheme in Low-Cost ATE
    Authors: 饒建奇;Rau, Jiann-Chyi;Chen, Gong-Han;Wu, Po-Han
    Contributors: 淡江大學電機工程學系
    Date: 2010-05-30
    Issue Date: 2011-10-23 21:21:31 (UTC+8)
    Publisher: IEEE
    Abstract: Generally speaking, the dependency data compression is very useful for Intellectual Property (IP) cores and SoC. We consider the shift-in power and compression ratio in low-cost ATE environment. We propose new compression architecture with fixed length for running ones. We suppose that the ATE has not repeated function and synchronization signal. In the results, when the complexity of VLSI circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest on ISCAS'89 benchmarks. The average of peak/WTC shift-in turns to 3×/6.6×, after comparing Selective Scan Slice (SSS) and our method. The average of hardware overhead is 6%.
    Relation: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, pp.1587-1590
    DOI: 10.1109/ISCAS.2010.5537430
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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