Low-power way-predicting cache using valid-bit pre-decision for parallel architectures

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Title:	Low-power way-predicting cache using valid-bit pre-decision for parallel architectures
Authors:	Chen, Hsin-Chuan;Chiang, Jen-Shiun
Contributors:	淡江大學電機工程學系
Date:	2005-03
Issue Date:	2011-10-23 21:20:15 (UTC+8)
Publisher:	Los Alamitos, California：Institute of Electrical and Electronics Engineers (IEEE)
Abstract:	Focusing on the way-predicting cache with sub-block placement, we propose a new cache scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary tag-subarrays and data-subarrays. By validbit pre-decision, it significantly helps in improving the average energy saving of the conventional waypredicting cache without valid-bit pre-decision, especially for with large associativity and small subblock size. Moreover, the proposed way-predicting cache can be applied to the parallel architecture systems to reduce the overall power consumption.
Relation:	Advanced Information Networking and Applications, 2005. AINA 2005. 19th International Conference on, vol.2, pp.203-206
DOI:	10.1109/AINA.2005.238
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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