English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 58317/91854 (63%)
造訪人次 : 14018247      線上人數 : 148
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70475

    題名: Low-power way-predicting cache using valid-bit pre-decision for parallel architectures
    作者: Chen, Hsin-Chuan;Chiang, Jen-Shiun
    貢獻者: 淡江大學電機工程學系
    日期: 2005-03
    上傳時間: 2011-10-23 21:20:15 (UTC+8)
    出版者: Los Alamitos, California:Institute of Electrical and Electronics Engineers (IEEE)
    摘要: Focusing on the way-predicting cache with sub-block placement, we propose a new cache scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary tag-subarrays and data-subarrays. By validbit pre-decision, it significantly helps in improving the average energy saving of the conventional waypredicting cache without valid-bit pre-decision, especially for with large associativity and small subblock size. Moreover, the proposed way-predicting cache can be applied to the parallel architecture systems to reduce the overall power consumption.
    關聯: Advanced Information Networking and Applications, 2005. AINA 2005. 19th International Conference on, vol.2, pp.203-206
    DOI: 10.1109/AINA.2005.238
    顯示於類別:[電機工程學系暨研究所] 會議論文


    檔案 描述 大小格式瀏覽次數
    Low-power Way predicting Cache Using Valid-bit Pre decision.pdf全文檔100KbAdobe PDF291檢視/開啟



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋