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    題名: Low power sigma delta modulator with dynamic biasing for audio applications
    作者: Chen, Hsin-liang;Lee, Yi-sheng;Chiang, Jen-shiun
    貢獻者: 淡江大學電機工程學系
    日期: 2007-08-07
    上傳時間: 2011-10-23 21:20:07 (UTC+8)
    出版者: IEEE
    摘要: In this paper, a low power sigma delta modulator with dynamic biasing technique is presented. According to the analysis of the operations of the switched-capacitor integrator, the folded-cascode operational amplifier can be designed with optimized biasing currents in three different phases to reduce power dissipations. The total power saving is 20% of the general one. A prototyping fourth order single-bit MASH 2-2 sigma delta modulator is designed with the technique of dynamic biasing to achieve dynamic range of 95 dB and peak signal-to-noise-and-distortion-ratio of 93 dB. The experimental circuit is designed in 0.35 mum 2P4M CMOS technology. The chip area is 3.11 mm2, and the power dissipation is only 5 mW from a supply voltage of 3 V.
    關聯: Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on, pp.159-162
    DOI: 10.1109/MWSCAS.2007.4488561
    顯示於類別:[電機工程學系暨研究所] 會議論文


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