Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/70472

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題名:	Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment
作者:	Wu, Po-han;Rau, Jiann-chyi
貢獻者:	淡江大學電機工程學系
日期:	2009-11
上傳時間:	2011-10-23 21:20:03 (UTC+8)
摘要:	In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing (Wang and Chakrabarty, 2008) and our method. The average of improvement/ hardware is 16%/6%.
關聯:	Test Conference, 2009. ITC 2009. International, pp.1
DOI:	10.1109/TEST.2009.5355633
顯示於類別:	[電機工程學系暨研究所] 會議論文

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