Low cost architecture for JPEG2000 encoder without code-block memory

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Title:	Low cost architecture for JPEG2000 encoder without code-block memory
Authors:	江正雄;Lin, Tsung-ta;Hwang, Ting-hao
Contributors:	淡江大學電機工程學系
Keywords:	2D-DWT;EBCOT;JPEG2000;RDO
Date:	2008-06-23
Issue Date:	2011-10-23 21:19:59 (UTC+8)
Publisher:	IEEE
Abstract:	The amount of memory required for code-block is one of the most important issues in JPEG2000 encoder chip implementation. This work tries to unify the output scanning order of the 2D-DWT and the processing order of the EBCOT and further to eliminate the code-block memory completely eliminated. We also propose a new architecture for embedded block coding (EBC), code-block switch adaptive embedded block coding (CS-AEBC), which can skip the insignificant bit-planes to reduce the computation time and save power consumption. Besides, a new dynamic rate distortion optimization (RDO) approach is proposed to reduce the computation time when the EBC processes lossy compression operation. The total memory required for the proposed JPEG2000 is only 2KB of internal memory, and the bandwidth required for the external memory is 2.1 B/cycle.
Relation:	Multimedia and Expo, 2008 IEEE International Conference on, pp.137-140
DOI:	10.1109/ICME.2008.4607390
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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