Latched CMOS differential logic(LCDL)for complex high-speed VLSI

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题名:	Latched CMOS differential logic(LCDL)for complex high-speed VLSI
作者:	Wu, Chung-yu;Cheng, Kuo-hsing
贡献者:	淡江大學電機工程學系
日期:	1989-09
上传时间:	2011-10-23 21:19:32 (UTC+8)
出版者:	IEEE
摘要:	A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL.
關聯:	Proceedings of 3rd international symposium on IC design and manufacture, pp.1324 - 1328
DOI:	10.1109/4.84952
显示于类别:	[電機工程學系暨研究所] 會議論文

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