High-speed four-phase CMOS logic for complex high-speed VLSI

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/70437

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题名:	High-speed four-phase CMOS logic for complex high-speed VLSI
作者:	Wu, Chung-yu;Cheng, Kuo-hsing;Wang, Jinn-shyan
贡献者:	淡江大學電機工程學系
日期:	1992-05
上传时间:	2011-10-23 21:17:53 (UTC+8)
出版者:	IEEE
摘要:	A novel four-phase dynamic logic, called high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically, the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and achieve a high operation speed. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to verify partly the results of circuit analysis and simulation. It is shown that the HS-PDCMOS has an operation speed about 2.5 to 3 times higher than that of the conventional four-phase dynamic logic. Moreover, the new logic has no problems of clock skew, race, and charge redistribution
關聯:	Proceedings of 1992 IEEE international symposium on circuits and systems, pp.1288 - 1291
DOI:	10.1109/ISCAS.1992.230269
显示于类别:	[電機工程學系暨研究所] 會議論文

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