High-speed four-phase CMOS logic for complex high-speed VLSI

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Title:	High-speed four-phase CMOS logic for complex high-speed VLSI
Authors:	Wu, Chung-yu;Cheng, Kuo-hsing;Wang, Jinn-shyan
Contributors:	淡江大學電機工程學系
Date:	1992-05
Issue Date:	2011-10-23 21:17:53 (UTC+8)
Publisher:	IEEE
Abstract:	A novel four-phase dynamic logic, called high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically, the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and achieve a high operation speed. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to verify partly the results of circuit analysis and simulation. It is shown that the HS-PDCMOS has an operation speed about 2.5 to 3 times higher than that of the conventional four-phase dynamic logic. Moreover, the new logic has no problems of clock skew, race, and charge redistribution
Relation:	Proceedings of 1992 IEEE international symposium on circuits and systems, pp.1288 - 1291
DOI:	10.1109/ISCAS.1992.230269
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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