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    題名: High-speed EBCOT with dual context-modeling coding architecture for JPEG2000
    作者: Chiang, Jen-Shiun;Chang, Chun-Hau;Lin, Yu-Sen;Hsieh, Chang-You;Hsia ,Chih-Hsien
    貢獻者: 淡江大學電機工程學系
    日期: 2004-05-23
    上傳時間: 2011-10-23 21:17:50 (UTC+8)
    摘要: This work presents a parallel context-modeling coding architecture and a matching arithmetic coder (MQ coder) for the embedded block coding (EBCOT) unit of the JPEG2000 encoder. The tier-1 of the EBCOT consumes most of the computation time in a JPEG2000 encoding system, and the proposed parallel architecture can increase the throughput rate of the context-modeling. To match the high throughput rate of the parallel context-modeling architecture, and efficient pipelined architecture for context-based adaptive arithmetic encoder is proposed. This encoder of JPEG2000 can work at 185MHz to encode one symbol each cycle. Compared with the conventional context-modeling architecture, our parallel architecture can decrease the execution time about 25%.
    關聯: Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on=2004年國際電子電機協會國際電路與系統研討會論文集, v.3, pp.865-868
    DOI: 10.1109/ISCAS.2004.1328884
    顯示於類別:[電機工程學系暨研究所] 會議論文

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