Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique

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題名:	Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
作者:	Chao, Ting-sheng;Lo, Yu-lung;Yang, Wei-bin;Cheng, Kuo-hsing
貢獻者:	淡江大學電機工程學系
日期:	2009-09
上傳時間:	2011-10-23 21:13:38 (UTC+8)
出版者:	IEEE
摘要:	This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-μm standard CMOS process with a 0.5V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610MHz with a 0.5V power supply voltage. At 550MHz, the measured rms jitter and peak-to-peak jitter are 8.01ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25mW and the active die area of PLL is 0.04mm2.
關聯:	The 35th European Solid-State Circuits Conference (ESSCIRC '09), pp.388 - 391
DOI:	10.1109/ESSCIRC.2009.5325983
顯示於類別:	[電機工程學系暨研究所] 會議論文

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