Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Proceeding > Item 987654321/70370

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Title:	Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture
Authors:	Hsia, Chih-Hsien;Chiang, Jen-Shiun;Huang, Ting-Wei
Contributors:	淡江大學電機工程學系
Keywords:	Discrete wavelet transform (DWT);Interlaced read scan algorithm(IRSA);Lifting-based DWT;Multiresolution;On-chip memory;Real-time
Date:	2005
Issue Date:	2011-10-23 21:13:22 (UTC+8)
Publisher:	雲林縣：雲林科技大學
Abstract:	This work presents novel algorithms and hardware architectures to improve the critical issue of 2-D discrete wavelet transform (DWT). On-chip memory cost is a very important problem in multimedia IC design. The architecture is based on the proposed interlaced read scan algorithm (IRSA) and pipeling scheme processing to achieve low-memory size and high-speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity. Meanwhile, our architecture can also provide embedded symmetric boundary extension function and regular data flow, and is suitable for VLSI implementation. It can be applied to real-time image/video operating of JPEG 2000 and MPEG-4 applications. A 2-D DWT VLSI test chip was designed and simulated by TSMC 0.35.mu. m 1P4M CMOS technology. The memory requirement of the N*N 2-D DWT is N and it can operate at 100MHz clock frequency.
Relation:	2005民生電子暨信號處理研討會論文集;Proceedings of Workshop on Consumer Electronics and Signal Processing, 6p.
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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