Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/70367

請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/70367

題名:	Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
作者:	Rau, Jiann-Chyi;Chen, Chien-Shiun;Wu, Po-Han
貢獻者:	淡江大學電機工程學系
關鍵詞:	SOC Testing;TAM;Testing Scheduling
日期:	2006-12-04
上傳時間:	2011-10-23 21:13:11 (UTC+8)
摘要:	Test access mechanism (TAM) and testing schedule for system-on-chip (SOC) are challenging problems. Testing schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a new method based on generalized rectangle packing, as two-dimensional packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test
關聯:	Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on, pp.1399-1402
DOI:	10.1109/APCCAS.2006.342462
顯示於類別:	[電機工程學系暨研究所] 會議論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
Design of Dynamically Assignmentable TAM Width.pdf		3640Kb	Adobe PDF	316	檢視/開啟
index.html		0Kb	HTML	219	檢視/開啟

在機構典藏中所有的資料項目都受到原著作權保護.

TAIR相關文章