Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs

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Title:	Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
Authors:	Rau, Jiann-Chyi;Chen, Chien-Shiun;Wu, Po-Han
Contributors:	淡江大學電機工程學系
Keywords:	SOC Testing;TAM;Testing Scheduling
Date:	2006-12-04
Issue Date:	2011-10-23 21:13:11 (UTC+8)
Abstract:	Test access mechanism (TAM) and testing schedule for system-on-chip (SOC) are challenging problems. Testing schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a new method based on generalized rectangle packing, as two-dimensional packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test
Relation:	Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on, pp.1399-1402
DOI:	10.1109/APCCAS.2006.342462
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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