Concurrent bit-plane coding architecture for EBCOT in JPEG2000

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題名:	Concurrent bit-plane coding architecture for EBCOT in JPEG2000
作者:	Chiang, Jen-shiun;Hsieh, Chang-yo;Liu, Jin-chan;Chien, Cheng-chih
貢獻者:	淡江大學電機工程學系
日期:	2006-05
上傳時間:	2011-10-23 21:12:12 (UTC+8)
出版者:	Institute of electrical and electronics engineers (IEEE)
摘要:	This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%
關聯:	Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp.4595-4598
DOI:	10.1109/ISCAS.2006.1693653
顯示於類別:	[電機工程學系暨研究所] 會議論文

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