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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70349

    Title: Concurrent bit-plane coding architecture for EBCOT in JPEG2000
    Authors: Chiang, Jen-shiun;Hsieh, Chang-yo;Liu, Jin-chan;Chien, Cheng-chih
    Contributors: 淡江大學電機工程學系
    Date: 2006-05
    Issue Date: 2011-10-23 21:12:12 (UTC+8)
    Publisher: Institute of electrical and electronics engineers (IEEE)
    Abstract: This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%
    Relation: Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp.4595-4598
    DOI: 10.1109/ISCAS.2006.1693653
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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