English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 49432/84393 (59%)
造訪人次 : 7453866      線上人數 : 70
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70311

    題名: An Efficient VLSI Architecture for 2-D DWT using Lifting Scheme
    作者: Chiang, Jen-Shiun;Hsia, Chih-Hsien
    貢獻者: 淡江大學電機工程學系
    日期: 2005
    上傳時間: 2011-10-23 21:09:42 (UTC+8)
    出版者: New York: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: In this paper, we propose a highly efficient VLSI architecture for 2-D lifting-based 5/3 filter discrete wavelet transform (DWT). The architecture is based on the pipelined and folding scheme processing to achieve near 100% hardware utilization ratio and reduce the silicon area. The advantages of the proposed DWT have the characteristics of higher hardware utilization, less memory requirement, and regular data flow. It is suitable for VLSI implementation and can be applied to real-time operating of JPEG2000 and MPEG4 applications.
    關聯: 2005年國際系統與信號研討會論文集=Proceedings of 2005 International Conference on System & Signals (ICSS2005), 4p.
    顯示於類別:[電機工程學系暨研究所] 會議論文





    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋