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    題名: A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
    作者: Cheng, Kuo-hsing;Hung, Cheng-liang;Chang, Chih-hsien;Lo, Yu-lung;Yang, Wei-bin;Miaw, Jiunn-way
    貢獻者: 淡江大學電機工程學系
    關鍵詞: CMOS integrated circuits;clocks;delta-sigma modulation;jitter;microwave generation;modulators
    日期: 2008-04-16
    上傳時間: 2011-10-23 21:08:47 (UTC+8)
    出版者: IEEE
    摘要: In this paper, a 6GHz spread-spectrum clock generator (SSCG) for Serial AT Attachment Generations 3 (SATA-III) is presented. By utilizing frequency modulation which employs digital MASH delta-sigma modulator and 33KHz triangular profile address generator, the SSCG achieves an output clock of 6GHz and 5000ppm down spread with a triangular waveform. The SSCG was designed based on TSMC 0.13μm 1p8m CMOS process. The power dissipation is 48mW under a 1.2V supply voltage. The peak-to-peak jitter of non spread-spectrum clock is 8ps, and the EMI reduction is 15dB with normal frequency spread modulation from 6GHz to 5.97GHz.
    關聯: 2008 The 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008),pp.1~4
    DOI: 10.1109/DDECS.2008.4538758
    顯示於類別:[電機工程學系暨研究所] 會議論文

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